|
Issue |
Title |
|
Vol 5, No 2 (2015) |
Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating |
Abstract
|
Sudhakar Jyothula, A. Mallikarjuna Prasad, Ajit Kumar Panda |
|
Vol 7, No 2 (2017) |
A Novel High Speed CMOS Flip-Flop Design in 16 nm Technology |
Abstract
|
P. Koti Lakshmi, Rameshwar Rao |
|
Vol 6, No 2 (2016) |
Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique |
Abstract
|
Archana Kumari, Navdeep Prashar |
|
Vol 3, No 1 (2013) |
Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects |
Abstract
|
Balaji B.S. |
|
Vol 3, No 1 (2013) |
A New High Speed Low Power 1 Bit Full Adder |
Abstract
|
Angshuman Chakraborty, Sambhu Nath Pradhan |
|
Vol 6, No 2 (2016) |
Design and Performance Trends of Low Power Sigma-Delta A/D Converters |
Abstract
|
Saima Bashir, Suhaib Ahmed, Vipan Kakkar |
|
Vol 6, No 1 (2016) |
Simulation Study of Tapered Shape FinFET |
Abstract
|
G. Musalgaonkar, A. Shrivastava, S. Singh, A. Acharya |
|
Vol 5, No 1 (2015) |
Characterization of High Speed Phase Frequency Detector Circuit |
Abstract
|
Nilesh D. Patel, Amisha P. Naik |
|
Vol 4, No 1 (2014) |
A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology |
Abstract
|
Viajyanand Krishnan, Sureshkumar N |
|
Vol 4, No 1 (2014) |
Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full Adder |
Abstract
|
A. Unmai |
|
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