Browse Title Index

Issue Title
Vol 5, No 2 (2015) 4-Bit Magnitude Comparator Design Using Different Logic Style Abstract
Vipul Mittal, Tanushree ., Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary
Vol 4, No 2 (2014) A Cuckoo Search based Approach for Solving Standard Cell Placement Problem Abstract
Amanpreet Singh, Maninder Kaur
Vol 6, No 1 (2016) A Differentiator Based on Second Generation Current Controlled Conveyor Abstract
A. Kumar, R. Pandey
Vol 3, No 1 (2013) A High Performance Reference Circuit with Optimized Input Offset Operational Amplifier using Device Mismatch Model Abstract
Kapil K Rajput, Sanjay Singh, Ravi Saini, Anil K Saini
Vol 4, No 3 (2014) A Low Power Variable Gain Amplifier for Biomedical Application Abstract
Dipesh Panchal, Amisha Naik, N M Devashrayee
Vol 4, No 1 (2014) A New Current Mode Quadrature Oscillator using Current Differencing Transconductance Amplifier (CDTA) Abstract
Md. Hassan, Sajal K. Paul
Vol 3, No 1 (2013) A New High Speed Low Power 1 Bit Full Adder Abstract
Angshuman Chakraborty, Sambhu Nath Pradhan
Vol 3, No 1 (2013) A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFET’s Threshold Voltage Extractor Abstract
Anil Kumar Saini, Megha Agarwal
Vol 6, No 2 (2016) A New TGC-Differential Input Stage to Modify Dynamic Comparator Abstract
Anurag Sharma, Gurinderpal Singh
Vol 3, No 3 (2013) A Novel 4:1 Multiplexer Design using Power Minimization Technique based Domino Logic Abstract
Vignesh M., Naveen R.
Vol 7, No 1 (2017) A Novel Approach Based On CHIP High Speed Optical Interconnection Network Abstract
Abhishek Sharma, Sudhir Kumar Sharma, Pramod Sharma
Vol 7, No 1 (2017) A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure Abstract
Ajoy Kumar Khan
Vol 4, No 2 (2014) A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture Abstract
Ashish S. Shende, Deepak R. Dandekar
Vol 4, No 1 (2014) A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology Abstract
Viajyanand Krishnan, Sureshkumar N
Vol 5, No 2 (2015) A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier Abstract
Kirti Sharma, Anushree .
Vol 7, No 2 (2017) A Novel High Speed CMOS Flip-Flop Design in 16 nm Technology Abstract
P. Koti Lakshmi, Rameshwar Rao
Vol 6, No 1 (2016) A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit Abstract
M. Hulkey, H. Upadhyay, K. Sujatha
Vol 5, No 3 (2015) A Real Time Authentication Framework Using Multi-Model Biometrics Abstract
Sneha Kurhekar, Harshvardhan Upadhyay
Vol 6, No 1 (2016) A Review for Power Optimization in MOS Devices using Different Logic Styles Abstract
M. Hulkey, H. Upadhyay, K. Sujatha
Vol 5, No 3 (2015) A Review on Charge Pump Circuits for PLL Applications Abstract
D. Shekhar, A. Raman
Vol 4, No 2 (2014) A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit Abstract
Ashish S. Shende
Vol 4, No 2 (2014) A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits Abstract
Harshvardhan Upadhyay
Vol 6, No 3 (2016) A Unified Ultra Low Power Architecture of Probabilistic Adder Based on GDI Technique Abstract
Srinibasa Padhy, Shivalal Patro, Monica Swain, Jitendra Kumar Das
Vol 5, No 3 (2015) All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey Abstract
Rajesh Yadav, Neeraj Kumar Shukla, Rajesh Gupta
Vol 1, No 2 - 3 (2011) An Explicit Approach to Compare Crosstalk Noise and Delay in VLSI RLC Interconnect Modeled with Skin Effect with Step and Ramp Input Abstract
Shilpi Lavania, Sunil Kumar Sharma
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