Sujatha, K., Department of Electronics & Telecommunication Engineering, SRCOE, Pune, Maharashtra, India, India
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Vol 6, No 1 (2016) - Review Articles
A Review for Power Optimization in MOS Devices using Different Logic Styles
Abstract -
Vol 6, No 1 (2016) - Research Articles
A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit
Abstract
ISSN: 2249 – 474X