Journal of VLSI Design Tools & Technology

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Table of Contents

Research Articles

A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit M. Hulkey, H. Upadhyay, K. Sujatha

PDF 1-5

Hardware Implementation of Configurable Multi Image Fusion SS. Malwadkar, WM. Mendre, SS. Agrawal

PDF 6-15

Simulation Study of Tapered Shape FinFET G. Musalgaonkar, A. Shrivastava, S. Singh, A. Acharya

PDF 21-31

Switched Capacitor Based RC Filter Jinal A. Prajapati, Prof. Mehul L. Patel

PDF 32-40

Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell P. Raikwal, V. Neema, A. Verma

PDF 41-48

Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence J. K. Arya, A. Raman

PDF 49-54

Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-Simulation Bhupendra Fataniya, Akash Mecwan, Dhaval Shah

PDF 55-61

Modeling of Voltage Buffer and Memristor Voltage Buffer Using 180 nm Technology Herman Al Ayubi, Navaid Z. Rizvi, Piyush K. Mishra

PDF 62-72

GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology Jubal Saji, Shoaib Kamal

PDF 77-78

A Differentiator Based on Second Generation Current Controlled Conveyor A. Kumar, R. Pandey

PDF 89-95

Review Articles

A Review for Power Optimization in MOS Devices using Different Logic Styles M. Hulkey, H. Upadhyay, K. Sujatha

PDF 16-20

Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell Jitendra Krishna Arya, Ashish Raman

PDF 73-77