Vol 5, No 2 (2015)

Open Access Open Access  Restricted Access Subscription or Fee Access

Table of Contents

Research Articles

Comparative Analysis of High Speed Comparator for A to D Converters
Priyesh P. Gandhi, Neha B. Rathod, N. M. Devashrayee
PDF
4-10
4-Bit Magnitude Comparator Design Using Different Logic Style
Vipul Mittal, Tanushree ., Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary
PDF
16-22
A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier
Kirti Sharma, Anushree .
PDF
23-28
Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating
Sudhakar Jyothula, A. Mallikarjuna Prasad, Ajit Kumar Panda
PDF
29-37
Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave
Pragya Sharma, Neeraj Kr. Shukla
PDF
42-48
Automated Access Backdoor for UVM_REG Layer
Seep Sethi, Neeraj Kr. Shukla
PDF
49-53
Characterization of High Performance Third Generation Current Conveyor using CMOS Technology
Megha M. Patel, Nilesh D. Patel
PDF
54-63
Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor
Nishtha K. Patel, Nilesh D. Patel
PDF
64-70
Design of 8 Bit High Speed Pipelined ADC
Shivani R. Patel, Priyesh P. Gandhi
PDF
71-80
Tuning Range, Phase Noise and Jitter Analysis of Current Starved Voltage Controlled Oscillator (VCO) for Digital PLL in 45 nm CMOS Technology
Bharat H. Nagpara
PDF
81-89

Review Articles

Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology
A. K. Pathrikar, Rajkumar S. Deshpande
PDF
1-3
Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter
Aakansha Barala, Pooja Sabherwal, Meenakshi Yadav
PDF
11-15
Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style
Megha Hulkey, Harshvardhan Upadhyay
PDF
38-41