Performance Analysis of DG FinFET for Ultralow-power Subthreshold Applications

Abstract

Subthreshold operating region of transistor shows huge potential toward satisfying demand of ultralow power (ULP) consumption from handheld portable devices. However, operating device with such small subthreshold leakage current as a switching current gives huge penalty in their operating frequency. For subthreshold operating region key design goal is to boost the speed of the device. DG FinFET device shows excellent device characteristics in subthreshold operating region. In this paper, 1-bit Full adder cell has been effectively analyzed. Since driving leakage current depends on operating temperature, performance analysis of Full adder is performed at different temperature. Simulation results show that dynamically connected static CMOS Full adder shows 43% advantage in delay over conv. static Full adder cell. DG FinFET-based Full adder cell shows significant advantage in delay as well as switching energy over static CMOS and DT CMOS-based Full adder.

Keywords: Subthreshold, power-delay product, Dg FinFET, DTCMOS