Implementation of Sub Parts of SAR ADC

Abstract

This paper describes the implementation of different sub parts of SAR ADC using a 180 nm CMOS technology in Mentor Graphics Tool. There are mainly four blocks in the SAR ADC. They are sample and hold, dynamic latch comparator, SAR logic and DAC logic. The simulation results show the transient analysis waveforms of different blocks of SAR ADC. Here to reduce power consumption dynamic latch comparator is used. Here the DAC logic is used for the feedback to comparator and it is made from the charge scaling capacitor. This design is for low power and low area consumption in chip or circuit design. This SAR ADC is high speed switching and low power consumption with compares to any other ADC.

Keywords: CMOS, sample and hold, dynamic latch comparator, SAR logic, DAC logic, mentor graphics

Cite this Article

Patel Purvi J, Gandhi Priyesh P. Implementation of sub parts of SAR ADC. Journal of VLSI Design Tools and Technology. 2015; 5(3): 139–147p.