Implementation and Analysis of Linear Electrical Networks using Interval Arithmetic on FPGA’s

Abstract

Interval arithmetic provides better method for monitoring and controlling errors in scientific calculations. Interval arithmetic can be used to obtain an analysis of linear electrical networks using hardware description language (HDL). In this paper the mean value theorem is used to analyze the circuits and implemented on hardware. The mean value theorem is applied for three different circuits i.e., for first order, second order and third order analog circuits. The experimental result confirms that using HDL performance is better as compared to software tools. It requires more than 106 times less delay time as compared to other available software tools. Using our proposed approach, a significant performance improvement is achieved over software implementation methods.

Keywords: Linear equations with dependent elements, mean value forms, linear electrical networks, global optimization, HDL-VHDL