Issue | Title | |
Vol 6, No 2 (2016) | Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power | Abstract |
Vijay Savani, N. M. Devashrayee | ||
Vol 2, No 1 (2012) | High-speed CMOS ADCs Design | Abstract |
Prashant Singh, Narendra Bahadur Singh | ||
Vol 6, No 3 (2016) | Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy | Abstract |
Shashank Gautam, Pramod Sharma | ||
Vol 3, No 3 (2013) | Design and Analysis of Source Current Effect on Preamplifier-Positive Feedback-based CMOS Comparator Using 90 nm Technology | Abstract |
Vijay Savani, N. M. Devashrayee | ||
1 - 4 of 4 Items |
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