Reduced Partial Product Booth Multiplier with An Effective Error Compensation Circuit

著者

  • Resma Chandran. V.P Department of Electronics and Communication, Mangalam College of Engineering, Affiliated to MG University, Kottayam, Kerala, India
  • Simi P Thomas Department of Electronics and Communication, Mangalam College of Engineering, Affiliated to MG University, Kottayam, Kerala, India
  • Sunu Ann Thomas Department of Electronics and Communication, Mangalam College of Engineering, Affiliated to MG University, Kottayam, Kerala, India

要旨

Reduced partial product Booth multiplier is mainly used in multimedia and digital signal processing (DSP) systems. In this paper, design of reduced partial product (constant-width) Booth multiplier is introduced. Here the least significant bit (LSB) of partial product matrix of Booth multiplier is removed and an error compensation function is derived for reducing truncation error. A simple error compensation circuit (SC generator) is also introduced to reduce the computations that make the truncation error value to be zero. In the previous multipliers, direct truncation method produces large truncation error; in the proposed system that generates final constant-width product by using a simple circuit, is denoted as SC-generator. Reduced partial product Booth multiplier can also improve peak signal-to-noise ratio (PSNR) of output images by 2 dB and 1.1 dB, respectively.  Keywords: error compensation circuit, constant-width multiplier, mean error, mean-square error, modified Booth multiplierCite this Article Resma Chandran V.P., Simi P. Thomas, Sunu Ann Thomas. Reduced Partial Product Booth Multiplier with an Effective Error Compensation Circuit. Trends in Electrical Engineering (TEE). 2015; 5(2): 42–49p.

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発行日

2015-07-04

巻号

巻 5 号 2 (2015)

セクション

Research Articles

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