Vol. 7 No. 1 (2017)

Research Articles

• Implementation of Carry Select Adder with Reduced Area Scheme

  Pinaki Satpathy

  1-5

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• A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure

  Ajoy Kumar Khan

  6-17

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• Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops

  Gunjankumar R. Modi, Priyesh P. Gandhi, Nilesh D. Patel

  18-28

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• Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture

  Boda Venkata Lakshmi, Boggavarapu Satish Kumar

  29-34

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• Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology

  Rahulkumar S. Suthar, Priyesh P. Gandhi

  35-40

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• A Novel Approach Based On CHIP High Speed Optical Interconnection Network

  Abhishek Sharma, Sudhir Kumar Sharma, Pramod Sharma

  41-48

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• Enhancement in RMPA Parameters using Slotted Rhombus Connected Square Shaped Antenna with left Handed Metamaterial

  RamKishor Sharma, Mahendra Kumar Pandey, Sandeep Kumar Agrawal

  49-54

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