Journal of VLSI Design Tools & Technology
Journal of VLSI Design Tools & Technology (JoVDTT) is an international e Journal focused towards the rapid publication of fundamental research papers on all areas of VLSI Design Tools & Technology. Focus and Scope Covers Analog/Digital Integrated Circuits & Systems VLSI Architectures, Algorithms, Methods & Tools for Modeling Simulation, Synthesis & Verification of Integrated Circuits and Systems Embedded Systems; High-Level Synthesis for VLSI Systems Test Generation Algorithms, Physical Design Systems Engineering Heterogeneous Systems
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FPGA Implementation of Multiplier-less FIR Filter to Handle Higher Frequency Signals
Filtering a signal in general involves spectrum modification by blocking or allowing the required portions of the spectrum based on the frequency requirement. Filters are designed based on the requirements for manipulating the signal for a desired application. This paper focuses on the existing architectures for developing FIR filters and also describes a new method to develop a multiplier-less filter which is suitable to implement any type of FIR filter. The proposed architecture helps in area reduction and it also increases the computational speed. The proposed architecture is most suited for FPGA implementation as it does not use the conventional multiply and accumulate operations which involve the usage of more number of multipliers and adders. The proposed architecture can be used for higher frequency signals which involve a large number of filter coefficients. Keywords: FIR filter, MAC, DA based filter Cite this Article Srividya P. FPGA Implementation of Multiplier-less FIR Filter to Handle Higher Frequency Signals. Journal of VLSI Design Tools & Technology. 2017; 7(2): 45–53p.
Voltage Mode Second Order Multifunction Inverse Filter Using Single OTRA
In this paper, a single operational transresistance amplifier (OTRA) based voltage mode single input single output (SISO) second order multifunction inverse filter configuration is proposed. The configuration offers an electronically tunable pole frequency and a quality factor of 1 which remains constant for any value of pole frequency. All the five inverse filters viz. inverse low-pass, inverse high-pass, inverse bandpass, inverse notch and inverse all-pass are realized from the same topology. Workability of the design is verified by PSPICE using 0.5 um CMOS process parameters provided by MOSIS (AGILENT). Keywords: OTRA, SISO, multifunction inverse filter Cite this Article Nidhi Yadav, Paul Sajal K. Voltage Mode Second Order Multifunction Inverse Filter Using Single OTRA. Journal of VLSI Design Tools and Technology. 2017; 7(2): 7–12p.
Effect of Doping and Crystal Orientation on Channel Current for Multigate Si Nanowire FET
This manuscript investigates the effects on channel current by varying gate orientation as well as channel doping concentration for Si nanowire FET. Both gate and drain voltage biasing are considered here for showing variations in channel current. After analyzing simulation results for silicon 100 and 110 crystal orientation it has been found that gate all around and top gate only show significant increment in channel current on different occasions over other gate structures. Keywords: FinFET, NWFET, GAA, multi gate Cite this Article Habib Muhammad Nazir Ahmad, Mustafa Mohammad Shaky. Effect of Doping and Crystal Orientation on Channel Current for Multigate Si Nanowire FET. Journal of VLSI Design Tools & Technology. 2017; 7(2): 20–29p.
A Novel High Speed CMOS Flip-Flop Design in 16 nm Technology
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption as compared to the other CMOS design styles. This paper proposes a novel high speed flip flop design in 16 nm technology. The design was compared with the existing low power techniques in terms of power, and delay (clk-Q and D-Q). The proposed design was found to be 20% fast as compared to basic 9T True single phase clocked (TSPC) flip-flop and 2.7% fast as compared to Yuan/Svensson D-flip flop and consumes 8.87% less power. Keywords: High speed D-FF, domino logic, low power design, power delay product (PDP), energy delay product (EDP) Cite this Article Lakshmi PK, Rao R. A Novel High Speed CMOS Flip-Flop Design in 16 nm Technology. Journal of VLSI Design Tools & Technology. 2017; 7(2): 37–44p.
Single OTRA Based First Order Multifunction Filter
A first order voltage mode (VM) multifunction filter has been proposed in this paper. It uses a single operational trans-resistance amplifier (OTRA) and few passive components. The same topology can be used for the implementation of first order low pass (LP), high pass (HP) and all pass (AP) filter functions. The LP and HP filters proposed here have variable gains and orthogonal tunability of gain and cut-off frequency. The theoretical results are verified with PSPICE simulation using 0.5 µm CMOS technology. Keywords: Operational trans-resistance amplifier, voltage mode, multifunction filter Cite this Article Deepa Kumari, Sajal K. Paul. Single OTRA Based First Order Multifunction Filter. Journal of VLSI Design Tools and Technology. 2017; 7(2): 1–6p.
Low-Offset High Speed CMOS Voltage Comparator
A Low-Offset High Speed CMOS comparator using dynamic latch, suitable for high-speed Analog-to-Digital Converter (ADC) with high speed and low offset dissipation is presented. The design is intended to be implemented in Low-offset high speed CMOS Voltage Comparator. This circuit combines the good features of the resistive dividing comparator and the differential current sensing comparator. The design has been carried out in Tanner EDA tools, the schematic simulation is done using Schematic Editor (T-spice) using 0.18μm CMOS technology.It is found that the Offset is least dissipated in 1.8V which is 0.356mW, but it has the longest propagation delay of 1.33 ns. Keywords: dynamic latch, CMOS comparator, differential current sensing, low-offset Cite this Article Joshii Rohitkumar M, Gandhi Priyesh P. Low-Offset High Speed CMOS Voltage Comparator. Journal of VLSI Design Tools and Technology. 2017; 7(2): 13–19p.
Comparative Analysis of Various Existing NT SRAM Cells with High Speed Low Power 8T SRAM Cell
The high speed along with low leakage devices are in demand in current CMOS technology era. With the advancement of technology, it is a big challenge to keep the balance of sizing and other parameters such as leakage current, delay and stability. In this paper, different cell topologies 6T, 7T, 8T, 9T and 10T SRAM cell are discussed and compared with the proposed single ended 8T SRAM cell. The comparison has been carried out on different parameters like, read and write access delay, write margin, read and hold stability, and leakage current. The analysis depicts that proposed cell shows less read and write access delay which is 114.13 and 38.56 ps respectively. The 6T SRAM cell consumes highest leakage current 349.104 nA, whereas the proposed cell consumes 671.22 pA. The 9T SRAM and 10T SRAM cell shows the highest write margin, read and hold static margin. The write margin, read and hold static margin for 9T SRAM and 10T SRAM cell are 388mv, 367mv, 373mv and 387mv, 368mv, 387mv respectively; whereas for proposed 8T cell it is 310mv, 343mv and 329mv. Keywords: CMOS technology, SRAM, stability, single ended Cite this Article Raikwal P, Neema V, Verma A. Comparative Analysis of Various Existing NT SRAM Cells with High Speed Low Power 8T SRAM Cell. Journal of VLSI Design Tools & Technology. 2017; 7(2): 30–36p.
Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology
This paper presents folding and interpolating ADC with resolution of 5 bit. The simulation result is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. This folding and interpolating ADC consumes less power than other and it is 10 mW. The rate of conversion is 50 MS/S. So, it is suitable for low power application and medium resolution portable devices. Keywords: Folding ADC, interpolating, ADC, low power comparator Cite this Article Suthar Rahulkumar S, Gandhi Priyesh P. Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology. Journal of VLSI Design Tools & Technology. 2017; 7(1): 35–40p.
Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture
Content Addressable Memory (CAM) is a storage unit used for faster accessing of lookup table that reduces processing time for search operation. It is mainly used very-high-speed searching applications like computer networking devices. The MAC address table is implemented with a CAM so that the destination port can be easily detected by reducing the switch’s latency. CAM gets its high speed of operation by parallel search mechanism. This paper proposes a CAM with master slave match line architecture. It uses a 128 ´ 8 CAM with reduced voltage swing to minimize power consumption. Complete memory is searched simultaneously for decreasing the time needed for search operation. Hence, computational time gets reduced appreciably. The performance of CAM is estimated by computing the power consumption and match delay. The results are analysed and compared for various match cases. HSPICE along with Cosmoscope is used to simulate and view the waveforms respectively. Keywords: HSPICE, CAM, Match delay and MSML Cite this Article Boda Venkata Lakshmi, Boggavarapu Satish Kumar. Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture. Journal of VLSI Design Tools and Technology. 2017; 7(1): 29–34p.
Enhancement in RMPA Parameters using Slotted Rhombus Connected Square Shaped Antenna with left Handed Metamaterial
In this paper, rectangular micro strip patch antenna (RMPA) along with metamaterial which has design of “slotted rhombus connected with rectangular shaped cover structure” is proposed at height of 3.2 mm from the ground plane. The RMPA with proposed metamaterial structure is designed to resonate at 2.7 GHz frequency. This work is mainly focused on increasing the potential parameters of micro strip patch antenna. Proposed metamaterial design structure significantly reduces the return loss and increases the bandwidth and directivity of the antenna as compared to RMPA alone. The bandwidth is increased up to 27.9 MHz in comparison to RMPA alone. The return loss of proposed antenna is reduced by 18 dB by incorporating the proposed metamaterial structure. For simulation purpose, CST-MWS software has been used. Keywords: Rectangular micro strip patch antenna, metamaterial, bandwidth, return loss Cite this Article Ram Kishor Sharma, Mahendra Kumar Pandey, Sandeep Kumar Agrawal. Enhancement in RMPA Parameters using Slotted Rhombus Connected Square Shaped Antenna with Left Handed Metamaterial. Journal of VLSI Design Tools & Technology. 2017; 7(1): 49–54p.
A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure
Floor planning is a key issue in VLSI physical plan. The floor planning issue can be defined as that a given arrangement of 3D rectangular pieces while limiting reasonable cost capacities. Here, we are focusing on the minimization of the aggregate volume of 3D bite the dust. In this paper, another initial topological structure is presented utilizing weighted coordinated chart of a floor planning issue in 3D VLSI physical plan. In any case, here the principle question is whether this structure is compelling (or not). For this, the possibility of another calculation is proposed to limit the volume of 3D bite the dust in floor planning issue utilizing this new representation procedure. It is intriguing to see that our proposed structure is likewise proficient to ascertain the aggregate volume and position of the dead spaces if they exist. The trial consequences of the new calculation are appeared in the following. Keywords: Floor planning, 3D rectangular block, weighted directed graph, topological structure, dead space Cite this Article Ajoy Kumar Khan. A Novel Approach for 3D Floor planning in VLSI with Minimum Dead Space using a New Topological Structure. Journal of VLSI Design Tools and Technology. 2017; 7(1): 6–17p.
Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops
This paper presents phase frequency detector using different gates like AND, NOR and NAND and comparative simulation result analysis is carried out. The simulation is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. NAND based PFD has lowest power consumption then other and it is 4.2587 µW at 1 GHz Frequency and dead zone to 18 ps which means having approximately zero dead zone problem. So, it is suitable for low power application. Keywords: Dead zone, glitch period, phase-locked loops, phase frequency detector Cite this Article Gunjankumar R. Modi, Priyesh P. Gandhi, Nilesh D. Patel. Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops. Journal of VLSI Design Tools and Technology. 2017; 7(1): 18–28p.
A Novel Approach Based On CHIP High Speed Optical Interconnection Network
On-chip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately solve the communication problem and obtain high-performance integrated circuits. On-chip interconnects are an important performance limiting factor in present day VLSI design. Performance optimization has always been a critical step in the designing of integrated circuits. In this paper, an optical interconnect in 1550 nm range is being implemented using opti-system software. A novel approach is being established in this paper for an optical interconnect. Keywords: Integrated optoelectronic circuits, optoelectronics, optical interconnects (ICs), silicon photonics Cite this Article Abhishek Sharma, Sudhir Kumar Sharma, Pramod Sharma. A Novel Approach Based On-Chip High Speed Optical Interconnection Network. Journal of VLSI Design Tools & Technology. 2017; 7(1): 41–48p.
Implementation of Carry Select Adder with Reduced Area Scheme
<!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:TrackMoves /> <w:TrackFormatting /> <w:PunctuationKerning /> <w:ValidateAgainstSchemas /> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:DoNotPromoteQF /> <w:LidThemeOther>EN-IN</w:LidThemeOther> <w:LidThemeAsian>X-NONE</w:LidThemeAsian> <w:LidThemeComplexScript>X-NONE</w:LidThemeComplexScript> <w:Compatibility> <w:BreakWrappedTables /> <w:SnapToGridInCell /> <w:WrapTextWithPunct /> <w:UseAsianBreakRules /> <w:DontGrowAutofit /> <w:SplitPgBreakAndParaMark /> <w:DontVertAlignCellWithSp /> <w:DontBreakConstrainedForcedTables /> <w:DontVertAlignInTxbx /> <w:Word11KerningPairs /> <w:CachedColBalance /> </w:Compatibility> <m:mathPr> <m:mathFont m:val="Cambria Math" /> <m:brkBin m:val="before" /> <m:brkBinSub m:val="--" /> <m:smallFrac m:val="off" /> <m:dispDef /> <m:lMargin m:val="0" /> <m:rMargin m:val="0" /> <m:defJc m:val="centerGroup" /> <m:wrapIndent m:val="1440" /> <m:intLim m:val="subSup" /> <m:naryLim m:val="undOvr" /> </m:mathPr></w:WordDocument> </xml><![endif]--> Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So, adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry select adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple carry adder (RCA) in the structure. To reduce the area of CSLA, a CSLA with binary to excess-1 converter is already designed which reduces the area of adder. But there are other techniques to design a CSLA to reduce its area. One of such technique is using an add-one circuit technique. This paper proposes the design of square root CSLA (SQRT CSLA) using add one circuit with significant reduction in area. Keywords: CSLA, combinational circuit, adders, BEC, D-latch Cite this Article Pinaki Satpathy. Implementation of Carry Select Adder with Reduced Area Scheme. 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A Unified Ultra Low Power Architecture of Probabilistic Adder Based on GDI Technique
In the present arena of technology scaling, the power consumption in the deep submicron technology plays a pivotal role as the transistor counts increases dramatically. Therefore, the need of the hour is to focus on power dissipation. The rate of occurrences of errors in the present VLSI scenarios has become higher and inevitable, and is increasing along with technology scaling. Eradicating all the errors is a cumbersome task; still a semi accurate result in better performance instead of accurate one can be accepted in some specific applications. An error tolerance adder is one such application specific adder to overcome the power delay trade-off by eradicating carry propagation and introducing a little error. To further enhance its efficiency and performance, GDI technique is introduced. In this paper, the GDI based architecture of probabilistic error tolerant adder (III) has been introduced, thus inferring the simulation with much more reduced power, delay and enormously enhanced performance over conventional adder. Keywords: Error tolerance, gate diffusion input, full adder Cite this Article Srinibasa Padhy, B.S.Patro, Monica Swain et al. A Unified Ultra Low Power Architecture of Probabilistic Adder Based on GDI Technique. Journal of VLSI Design Tools &Technology. 2016; 6(3): 45–55p.
Design of High-Speed and Low-Power Carry Skip Adder
In this brief, we present a high speed and lower power consumption carry skip adder (CSKA) architecture compared with the conventional one. The increment of speed is attained by implementing concatenation and incrementation strategy to improve the efficiency of the conventional CSKA (Conv-CSKA) architecture. Instead of make use of multiplexer logic, the proposed architecture makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) combination gates for the carry skip logic. The structure possibly designed with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and power parameters of the adder. This expansion utilizes a modified parallel structure for increasing the slack time, and enabling further voltage reduction. The proposed architectures are evaluated by comparing their speed, power, and area with those of other adders using 90-nm and 45-nm static CMOS technology. Keywords: Carry skip adder (CSKA), high performance, incrementation, concatenation Cite this Article Venkatrao and Krishna. Design of High-Speed and Low-Power Carry Skip Adder. Journal of VLSI Design Tools and Technology. 2016; 6(3): 35–44p.
Survey of System-on-Chip Modular Test Approach
industry to develop new design and reuse methodologies referred as System-on-chip (SoC) design. These typically integrate heterogeneous mix of various complex analog and digital cores, with all their necessary electronic circuitry. The recent advancements have led to the use of the 3D structures (3D-SOCs) that brought along the benefits of higher performance, minimum average interconnect length, reduced power and smaller footprint. These revolutions have not only brought in new issues of design but also their testing which is becoming the major bottleneck in determining the overall system cost and a defect free delivery to market in time. To facilitate the testing of cores lying inside such complex SOCs modular approach, concurrency in test application are the only viable ways. However these come at their own costs of constraints like power, test bandwidth, resources like “through silicon vias”, BIST etc. This paper first discusses in general the various challenges in testing of core-based system chips, the associated test factors and modular test approach. It is further followed up by the various ways of addressing the challenges and the corresponding research areas. Keywords: System on chip test, test data compression, test access architecture, embedded core based design, system on chip test architecture Cite this Article Vohra and Singh. Survey of System-on-Chip Modular Test Approach. Journal of VLSI Design Tools & Technology. 2016; 6(3): 56–70p.
Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications
In this paper, two designs of flash analog to digital converters (ADCs) based on threshold inverter quantization (TIQ) technique are presented. The parallel threshold inverter quantization (PTIQ) flash ADC exploits the advantage of reduction in capacitance and power consumption if the transistors are placed in parallel. Another design called low voltage tunable body bias (LVTBB) PTIQ ADC operates at near threshold voltage level to minimize the power consumption. The PTIQ and LVTBB ADC designs attain Figure of merit of 0.09625 picoJoule/conversion (pJ/conv) and 0.06 pJ/conv respectively which is comparable to the existing state of art ADCs. Keywords: ADC, TIQ, PTIQ, LVTBB, threshold voltage, power consumption Cite this Article Ankush Chunn and Rakesh Kumar Sarin. Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications. Journal of VLSI Design Tools and Technology. 2016; 6(3): 71–87p.
VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter
As the technology progresses, a large number of devices can be incorporated into a single chip. So, the communication between these devices becomes critical. The network-on-chip (NoC) is a technology used for such communication and overcomes the constraints of traditional bus-based system-on-chip (SoC). Router is the backbone of NoC and determines the performance to a great extent. This paper focuses on the implementation of five port virtual channel router which is considered as promising router architecture for NoC. The major building blocks of router are virtual channel buffer architecture, fairness arbiter, i.e. RRA and a crossbar switch. An arbiter employs a scheduling algorithm which is used to decide which one of several requests would be serviced. The round robin arbiter is based on the assignment of a fixed time slot per requester. The source code is written in VHDL. The proposed router is synthesized and simulated in Xilinx ISE Design Suite 13.1. Keywords: Network-on-chip (NoC), system-on-chip (SoC), intellectual property (IP), processing element (PE), network interface (NI), virtual channel (VC), round robin arbiter (RRA) Cite this Article Wanjari Minakshi M, Pankaj Agrawal, Ravindra Kshirsagar. VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter. Journal of VLSI Design Tools & Technology. 2016; 6(3): 88–93p.
Design of FPGA Based ALU Using Reversible Logic Gates
Reversible or information misfortune less circuits has applications in computerized signal handling, correspondence, PC design and nanotechnology. Reversible technique is utilized to minimize heat that happens in traditional circuits by keeping the loss of data. This paper proposes a reversible configuration of an ALU. This ALU comprises of eight operations, five are of arithmetic category and three are from logical category operations. An arithmetic operations incorporate add, sub, increase by one, decrement by one, multiply whereas logical operations incorporate AND, OR, and XOR. Each module is being composed utilizing the fundamental reversible basic gates. The Area analysis, power analysis and delay analysis of the different sub modules is performed and a correlation with the conventional circuits is likewise completed. We designed the ALU in Verilog HDL and Simulated by using Modelsim 6.4c Software. The proposed ALU Design is synthesized by Xilinx and Implemented into FPGA Spartan 2 XC2S200PQ208. Keywords: VLSI, quantum cost, ALUt, revesible gate, reversible logic Cite this Article Vishal A. Wankhede, Ramprasad M. Gawande. Design of FPGA Based ALU Using Reversible Logic Gates. Journal of VLSI Design Tools & Technology. 2016; 6(3): 15–21p.
Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers
More sophisticated designs of communicating devices are required with tremendous scaling in MOS. Mixers play a vital role in all radio transmitters and receivers. To improve the sensitivity of the receivers, the low noise amplifiers are designed with very high gain. Higher gain of amplifier saturates the preceding sections and forces them to operate in the nonlinear region. MOS based Single Balanced and Double Balanced mixers are the most common designs for down conversion mixer. The paper discusses the linearity issue for both the traditional mixers. Basic definition of linearity is explained and the mathematical analysis based on Taylor’s series expansion is carried out for single and double balanced mixers. Keywords: Linearity, IIP3, mixer, mathematical analysis, amplifiers Cite this Article Akash I. Mecwan, N M Devashrayee. Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers. Journal of VLSI Design Tools & Technology. 2016; 6(3): 22–27p.
Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier
Multiplication, a very important arithmetic operation, is finding a great use these days in various applications (especially DSP, multimedia and image processing). Due to advances in technology and increasing needs for high speed calculations, it has become really necessary and important to design a fast efficient multiplier. A productive method to speed up the multiplication is reduction in the Partial Product (PP) array. In this paper the design of 8, 16 and 32 bit RNS multiplier based on Radix-4 Booth encoding is presented. The results of simple Booth multiplier are compared to a Booth encoded Residue Number System (RNS) multiplier. A significant improvement in terms of speed and area utilization is observed when Booth is applied to RNS. Pipelining has been incorporated in the architectures to boost the speed further. The designs are described in Verilog HDL, simulated and synthesized on Xilinx 14.5, targeted on Spartan 3E FPGA device. Keywords: Booth algorithm, Radix-2, Radix-4, Radix-8, multiplication, Residue Number System, pipelining Cite this Article Saguna Goel, Sakshi Bajaj, Amanpreet Kaur. Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier. Journal of VLSI Design Tools & Technology. 2016; 6(3): 7–14p.
Development of System for Speech Enhancement using Combinational Adaptive LMS on Reconfigurable Platform
Low cost and robustness makes the least mean square (LMS) algorithm most popular. Improved adaptive filter performance can be obtained by combinational approach. In this paper, for speech enhancement, we used one of such approaches known as ‘filter combination’. As our simulation results show, Fixed-Sign LMS algorithm overcome other algorithms in terms of SNR and mean square error. Keywords: Adaptive filter, speech enhancement, windows, convex combination Cite this Article Pradip C. Bhaskar and Prochi S. Gosavi. Development of System for Speech Enhancement using Combinational Adaptive LMS On Reconfigurable Platform. Journal of VLSI Design Tools & Technology. 2016; 6(3): 28–34p.
Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy
The development of digital circuits, digital signal processors and other data processing integrated circuits, comparators are challenged by large area consumption. Comparator is most basic and fundamental component that performs comparison operation. This paper proposes a new approach to design an area efficient two bit magnitude comparator. Comparision is done on the grounds of area and power consumed between circuit designed by novel strategy and preexisting CMOS technique. The novel technique described in this paper is found to be effective and efficient to reduce the chip area. Keywords: Two bit, magnitude comparator, layout design, chip area, power consumption Cite this Article Shashank Gautam, Pramod Sharma. Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy. Journal of VLSI Design Tools & Technology. 2016; 6(3): 1–6p.
Implementation and Simulation of High Speed Dynamic Latch Comparator for ADC
<!--[if gte mso 9]><xml> <o:OfficeDocumentSettings> <o:RelyOnVML /> <o:AllowPNG /> <o:TargetScreenSize>1024x768</o:TargetScreenSize> </o:OfficeDocumentSettings> </xml><![endif]--> As per emerging issues in analog-mixed signal (AMS) design towards high speed and low power, limits the performance of high-speed applications. Circuit complexity, speed, offset voltage and resolutions are essential parameter of comparator that affects the Analog-to-Digital Converter (ADC) performance. Based on specifications, to achieve lower offset voltage and higher load drivability of latched comparator is presented. Moreover, the circuit is able to reduce power dissipation as the topology is based on latch circuitry. Resistor-divider structure was used to design a CMOS comparator in TSMC 180 nm technology due to advantage of high speed and no static power consumption. Here, systematic offset voltage is simulated. Achieved parameters are 1.2 GHz sampling rate, above 8 bit resolution, 98 ps propagation delay, 20 mV offset voltage and 77 µW power consumption. In the end, layout was prepared on pyxis (Mentor Graphics) tool. Keywords: Analog-to-Digital Converter (ADC), dynamic latch comparator, offset voltage, sampling rate Cite this Article Jatin A. Jajal, Mehul L. Patel. Implementation and Simulation of High Speed Dynamic Latch Comparator for ADC. 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