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Hardware Implementation of a Multistage Low Pass Sigma Delta Modulator

Kamel Alikhan Siddiqui, Ahtesham Ali

Abstract


The overall objective of this paper is to describe the design, simulation and observation of the hardware implementation of a multi stage low-pass sigma delta modulator on FPGA architecture using modelsim. The objective of this paper is shown first by describing a low-pass multistage for D/A sigma delta modulator. The next step involves a detailed evaluation of various accumulator based MASH structures which is then modeled in MATLAB and SIMULINK with the measurement of their characteristics and their non-idealties such as SNR ratio and PSD were calculated. The final part of the report is carefully evaluated and compared with the digital design; the selected prototype is a cascaded stage- 1-1 MASH (multi stage noise shaping structure) under FPGA. The major application of sigma delta modulators is found to be in N-PLL frequency synthesizers, using error feed back topology sigma delta modulator, which eliminates the limit cycles oscillations and tones, the designing of such an accumulator in FPGA can be a common use in the mentioned applications.

Cite this Article

Kamel Alikhan Siddiqui, Ahtesham Ali. Hardware implementation of a multistage low pass sigma delta modulator. Journal of Embedded Systems and Applications. 2015; 3(3): 13–21p.


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