|
Issue |
Title |
|
Vol 2, No 1 (2012) |
An FPGA-based Controller Design for Servo Actuator Using Xilinx System Generator and HDL Cosimulator |
Abstract
|
thangavel ananthan, M. V. Vaidyan, M. V. Varghese |
|
Vol 2, No 3 (2012) |
An Innovative Approach of the Analysis of the Low Noise of a CMOS-Based Amplifier for Analog Signal-based Applications |
Abstract
|
Rajinder Tiwari, R K Singh |
|
Vol 6, No 2 (2016) |
Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power |
Abstract
|
Vijay Savani, N. M. Devashrayee |
|
Vol 7, No 1 (2017) |
Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology |
Abstract
|
Rahulkumar S. Suthar, Priyesh P. Gandhi |
|
Vol 1, No 1 (2011) |
Analysis of Resource Utilization for a Floating-Point Complex Multiplication in FPGA |
Abstract
|
Anitha Mary, Dojin Domnic, Dr. K. Rajasekaran |
|
Vol 1, No 1 (2011) |
Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETs in Nanoregime |
Abstract
|
Neha Sharan, Ashwani Rana |
|
Vol 6, No 3 (2016) |
Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy |
Abstract
|
Shashank Gautam, Pramod Sharma |
|
Vol 5, No 2 (2015) |
Automated Access Backdoor for UVM_REG Layer |
Abstract
|
Seep Sethi, Neeraj Kr. Shukla |
|
Vol 1, No 1 (2011) |
Automatic Switch cum Fuse IC for Low Voltage, Low Power, High Performance Current Conveyors |
Abstract
|
Ashutosh Tripathi |
|
Vol 6, No 2 (2016) |
Challenges beyond 100 nm MOS devices |
Abstract
|
Savita Maurya, Sarita Shrivastava |
|
Vol 5, No 2 (2015) |
Characterization of High Performance Third Generation Current Conveyor using CMOS Technology |
Abstract
|
Megha M. Patel, Nilesh D. Patel |
|
Vol 5, No 1 (2015) |
Characterization of High Speed Phase Frequency Detector Circuit |
Abstract
|
Nilesh D. Patel, Amisha P. Naik |
|
Vol 6, No 1 (2016) |
Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell |
Abstract
|
P. Raikwal, V. Neema, A. Verma |
|
Vol 5, No 3 (2015) |
CMOS Gm-C IF Filter using SCA for Dual Band Receiver |
Abstract
|
Kehul A Shah, N M Devashrayee |
|
Vol 3, No 2 (2013) |
Cogeneration of Fast Motion Estimation Processor and Algorithms Using Loss Less Compression |
Abstract
|
M. Viji, S. Chitra |
|
Vol 5, No 2 (2015) |
Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor |
Abstract
|
Nishtha K. Patel, Nilesh D. Patel |
|
Vol 5, No 2 (2015) |
Comparative Analysis of High Speed Comparator for A to D Converters |
Abstract
|
Priyesh P. Gandhi, Neha B. Rathod, N. M. Devashrayee |
|
Vol 4, No 2 (2014) |
Comparative Analysis of Low-Power Adiabatic Techniques |
Abstract
|
Charu Rana, Priyanka Ohja |
|
Vol 6, No 2 (2016) |
Comparative Analysis of MOSFET, CNTFET and NWFET for High Performance VLSI Circuit Design: A Review |
Abstract
|
Sanjeev Kumar Sharma, Balwinder Raj, Mamta Khosla |
|
Vol 7, No 1 (2017) |
Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops |
Abstract
|
Gunjankumar R. Modi, Priyesh P. Gandhi, Nilesh D. Patel |
|
Vol 7, No 2 (2017) |
Comparative Analysis of Various Existing NT SRAM Cells with High Speed Low Power 8T SRAM Cell |
Abstract
|
P. Raikwal, V. Neema, A. Verma |
|
Vol 3, No 2 (2013) |
Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder |
Abstract
|
Ankit Mitra |
|
Vol 5, No 2 (2015) |
Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter |
Abstract
|
Aakansha Barala, Pooja Sabherwal, Meenakshi Yadav |
|
Vol 2, No 1 (2012) |
Decimator Design for Sigma-Delta ADC |
Abstract
|
Tripti Sharma, Prashant Singh, Narendra Bahadur Singh |
|
Vol 2, No 1 (2012) |
Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort and Transistor Sizing |
Abstract
|
Sampath Kumar V., neerja Singh |
|
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