Vol 6, No 3 (2016)

Open Access Open Access  Restricted Access Subscription or Fee Access

Table of Contents

Research Articles

Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy
Shashank Gautam, Pramod Sharma
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1-6
Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier
Saguna Goel, Sakshi Bajaj, Amanpreet Kaur
PDF
7-14
Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers
Akash I. Mecwan, N M Devashrayee
PDF
22-27
Development of System for Speech Enhancement using Combinational Adaptive LMS on Reconfigurable Platform
Pradip C. Bhaskar, Prachi S. Gosavi
PDF
28-34
A Unified Ultra Low Power Architecture of Probabilistic Adder Based on GDI Technique
Srinibasa Padhy, Shivalal Patro, Monica Swain, Jitendra Kumar Das
PDF
45-55
Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications
Ankush Chunn, Rakesh Kumar Sarin
PDF
71-87
VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter
Minakshi Motiram Wanjari, Pankaj Agrawal, Ravindra Kshirsagar
PDF
88-93

Review Articles

Design of FPGA Based ALU Using Reversible Logic Gates
Vishal A. Wankhede, Ramprasad M. Gawande
PDF
15-21
Survey of System-on-Chip Modular Test Approach
Harpreet Vohra, Amardeep Singh
PDF
56-70

Short Articles

Design of High-Speed and Low-Power Carry Skip Adder
Gutlapalli Venkatrao, Motkuri Krishna
PDF
35-44