Vol 6, No 2 (2016)

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Table of Contents

Research Articles

Challenges beyond 100 nm MOS devices
Savita Maurya, Sarita Shrivastava
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1-4
Layout Design, Fabrication and Characterization of n-Channel MOSFET
Savita Maurya, Sarita Shrivastava
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13-18
Design and Implementation of Low Power 8-bit Level Crossing ADC
Vaishali Gupta, Anil Kumar Gupta
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33-43
Design and RTL Implementation for AHBAPB Bridge on SoC
Shipra Sharma, Rakhi Nangia, Neeraj Kumar Shukla
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44-52
Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique
Archana Kumari, Navdeep Prashar
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53-61
Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM
Ashima Gandhi, Neeraj Kr. Shukla
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62-73
A New TGC-Differential Input Stage to Modify Dynamic Comparator
Anurag Sharma, Gurinderpal Singh
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74-85
Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power
Vijay Savani, N. M. Devashrayee
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86-98
Implementation and Simulation of High Speed Dynamic Latch Comparator for ADC
Jatin A. Jajal, Mehul L. Patel
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99-103
Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog
Ashima Gandhi
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104-112

Review Articles

Design and Performance Trends of Low Power Sigma-Delta A/D Converters
Saima Bashir, Suhaib Ahmed, Vipan Kakkar
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5-12
Comparative Analysis of MOSFET, CNTFET and NWFET for High Performance VLSI Circuit Design: A Review
Sanjeev Kumar Sharma, Balwinder Raj, Mamta Khosla
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19-32