A Novel High Speed CMOS Flip-Flop Design in 16 nm Technology

Abstract

Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption as compared to the other CMOS design styles. This paper proposes a novel high speed flip flop design in 16 nm technology. The design was compared with the existing low power techniques in terms of power, and delay (clk-Q and D-Q). The proposed design was found to be 20% fast as compared to basic 9T True single phase clocked (TSPC) flip-flop and 2.7% fast as compared to Yuan/Svensson D-flip flop and consumes 8.87% less power.

Keywords: High speed D-FF, domino logic, low power design, power delay product (PDP), energy delay product (EDP)

Cite this Article

Lakshmi PK, Rao R. A Novel High Speed CMOS Flip-Flop Design in 16 nm Technology. Journal of VLSI Design Tools & Technology. 2017; 7(2): 37–44p.