Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM

Abstract

Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single SoC makes verification of any SoC based design very critical. About 75–80% of the total design cycle time is spent in functional verification. To reduce this time and effort, hardware verification languages came into picture. The most popularly used HVL is system verilog which is based on object oriented programming concepts (OOPs). A design can be verified by writing a verification written in system verilog. Basically SV can be used for both design and verification, so it is termed as hardware design and verification language (HDVL). For improved reusability, efficiency and productivity, UVM (Universal Verification Methodology) came into picture, which is widely used in the verification industries nowadays. The work embodied in this paper presents the verification of advanced high performance bus-lite (AHB-Lite), which is the subset of advanced microcontroller bus architecture (AMBA). The verification environments are created using system verilog and UVM; and correspondingly functional coverage is computed for both. The functional coverage was found to be 100% in case of SV and UVM both. Functional and assertion coverage collectively in case of UVM was found to be 92.27%.

Keywords: Advanced microcontroller bus architecture, advanced high performance bus-lite, system verilog, system on chip, universal verification methodology, functional coverage, verification, hardware design and verification language

Cite this Article

Ashima Gandhi, Neeraj Kr. Shukla. Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM. Journal of VLSI Design Tools and Technology. 2016; 6(2): 62–73p.