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Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell

P. Raikwal, V. Neema, A. Verma


The demand of high density VLSI circuits has been increasing as the size of ICs is becoming small day by day. It has been seen that, to reduce active power dissipation in memory, the supply voltage reduction is necessary. Lowering the supply voltage is one of the most straightforward and effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power remarkably. The static power dissipation occurs in an idle mode of the circuit. In this paper, the analysis has been carried out on simple 6T SRAM cell using NMOS sleep transistor and current flowing through the sleep transistor in active and sleep mode has been taken out as well as the effect of changing the width of sleep transistor has been compared. In this work, a technique called ‘clustering technique’ has been proposed to reduce the active power requirement and the simulation has been done on 4X1 SRAM cell.  In this work first of all, the power dissipation of 4X1 SRAM cell without sleep is taken out. Then, the clustering technique is applied in which, first of all the cells are connected to an individual sleep then the sleep is shared between the two cells and after that all the four cells are connected to only one sleep. Therefore, the result with clustering technique shows an improved result than an individual sleep when connected to the SRAM cell. In this work, the SRAM cell without sleep transistor dissipates more power during different states as compared to SRAM cell with an individual sleep transistor. SRAM cell with sleep dissipates 26.65 % less power during write ‘1’ operation, 59.34 % less power during hold operation and 16.74 % less power during read operation. In clustering technique it has been further reduced, during write ‘1’ operation  the cell dissipates 49.09 % less power, while write ‘0’ operation it consumes 66.29 % less power, during read operation it dissipates 42.67 % less power as compared to the SRAM cell without sleep transistor.


Keywords: VLSI circuits, SRAM, NMOS, MTCMOS, 4X1 SRAM cell


Cite this Article


P. Raikwal, V. Neema1, A. Verma. Cluster based sleep transistor approach for low power 6T SRAM cell. Journal of VLSI Design Tools and Technology. 2016; 6(1): 41–48p.

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