Implementation of LMS Calibration Algorithm for 12-Bit Pipelined ADC

Abstract

As the technology is scaling, digital systems perform well with that but analog systems undergo degradation in their performance due to reduced gain. Thus, to improve their performance various calibration techniques are used. This paper implements one of such a digital calibration technique using digital signal processing, to compensate for the errors in 12-bit pipelined ADC with 1.5 bit/stage architecture at lower technology, without degrading the performance. The technique used is LMS (Least Mean Square) algorithm which is a digital foreground calibration technique for removing errors like gain error, capacitor mismatch and op-amp non-linearity. These errors are discussed in detail in this paper, their causes and effects and then the technique used to remove them. The algorithm is modeled in MATLAB and Xilinx ISE 14.5 using binary floating point multipliers and adders and further verified on FPGA. To reduce the delay and area used by floating point multipliers, Booth-8 algorithm is used and to compact the adders, carry save adders have been used. The calibration hardware built has a delay of 1656.921 ns for one-stage. After simulation, it is analyzed that DNL can be reduced from 1.45 LSB to 0.65 LSB and INL can be reduced from 136.45 LSB to 2.47 LSB using this calibration technique.

Keywords: Pipelined ADC, non-linearity correction, digital calibration, Least Mean Square (LMS) algorithm

Cite this Article

Vishal, Alpana Agarwal. Implementation of LMS Calibration Algorithm for 12-Bit Pipelined ADC. Journal of VLSI Design Tools and Technology. 2015; 5(3): 104–113p.