Roles and Responsibilities of Verification Language, Verification Methodology and Verification Tool for Design Verification of a DUT

Abstract

Verification of a design is as important as the design itself to make it work in a practical scenario. Verification phase is an important phase in System on Chip (SoC) design cycle and used to take 70% to 80% of the total design time. A verification environment may be prepared simply using a Hardware Verification Language (HVL) only without using any methodology or using a HVL with verification methodology. The question arises that if there is a core language designed specially to do verification of a design along with design then why do we need a methodology for verifying a design? Are there loop holes in the language? Does the language not suffice to write an efficient testbench? The answer lies somewhere in the middle that role and responsibilities are different for a language and a Methodology. We can say that there are many advantages of using a methodology to create verification environment than a language alone, however we can’t ignore the importance and role of a verification language for verification purposes. Here we will talk about different aspects of a verification language that is SystemVerilog (SV) and a methodology that is Universal Verification Methodology (UVM). We will discuss about SystemVerilog and UVM only among hardware verification languages and verification methodologies because these are the latest ones being used in the industries for verification purposes. We will also discuss the role of verification tool for verification of a design.