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Analysis of Resource Utilization for a Floating-Point Complex Multiplication in FPGA

Anitha Mary, Dojin Domnic, Dr. K. Rajasekaran


Complex multiplication is an important operation frequently used in the digital signal processing. This paper shows the resource utilization for a complex multiplication on Spartan3E by using a 9 bit floating point numbers. The proposed method clearly shows that resource utilization for complex multiplication is less than the IP cores proposed by the Xilinx Company. More over this paper shows how the significant and the exponent of the floating point number effect the resource utilization for a complex multiplication.  


Complex multiplication, Floating point, IP cores

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