System Level Modeling of ISMB Quadrature Transceiver

Abstract

In this paper, a new ISMB quadrature transceiver system-level design architecture is presented along with its referenced mathematical models and these were verified using state-of-the-art system modeling tools. Unlike a K-TEK’s receiver, it does not suffer from the timing and template matching problems, and it circumvents processing at high frequencies, thereby reducing the on-chip circuit complexity and power consumption. Hilbert transform has been used at the output of the demodulator for the envelope detection to get the more reliable desired signal that is also the uniqueness in the system. It also presents parallel approach to use a band-pass filter at the output of the demodulator to eliminate the d.c. component to get the desired signal. Matlab coding and Simulink system modeling were parallel done before the design of monolithic integrated circuit using CMOS technology to transfer the similar function on silicon and the objective is completed for most of the blocks. The system-level simulation, presented in this paper, shows the functional behavior of the proposed transceiver.