An Explicit Approach to Compare Crosstalk Noise and Delay in VLSI RLC Interconnect Modeled with Skin Effect with Step and Ramp Input

Abstract

As the technology is acquiring frequency of the Giga-hertz range noise and delay calculations and avoidance of such factors in VLSI interconnects have become dominant to be considered. This paper represents a comparison between the crosstalk noise voltage level measured when the RLC on-chip interconnect was modeled when the skin effect was considered under step input and the crosstalk voltage measured when the RLC line was modeled with skin effect under ramp input. In this paper, we have proposed a detailed discussion about the relevance of the input applied to any interconnect that can affect the whole system integrity. The importance and dominance of the skin effect cannot be ignored. But apart from the high frequency effect like skin effect and proximity effect, it is also very important to observe that these factors may harm the system integrity if the wrong input is applied. This paper reflects the approximated noise and delay variations in different cases of inputs applied to the Global RLC interconnect.