Analysis of LSDCCFF at 0.09 µm Technology

Abstract

The traditional low swing differential conditional capture flip-flop (LSDCCFF) for LC resonant clock distribution network has wide range of applications but has poor power consumption. These characteristics can be improved by using the modified LSDCCFF. This paper presents the design of modified LSDCCFF with less delay and low operating power. The implementation of the circuit is done using LSDCCFF. By using voltage scaling technique, the average power consumption can be reduced. An analysis of the LSDCCFF is presented. The design has been implemented in 0.09 µm technology.The modified LSDCCFF exhibits a D-Q delay of 1.32 ns, and average power consumption of 8.87µw.

Keywords: Delay, flip-flop, low-swing, average power, SR latch