Power Consumption Reduction using Microarchitecture Techniques for Modern Multicore Microprocessors

Abstract

The development in the semiconductor technology is helping the designer to make the systems as compact as possible. We are moving towards 14 nm fabrication technology. The technology scaling is going much down but it is also the reason to bring several crucial issues on the surface which is very difficult to handle. The various advance processor architecture design concepts helped in increasing speed by keeping the power consumption under limit. The power consumption is a crucial parameter which is going to affect the computer architecture philosophy largely in the near future. Everyone needs highest performance with lowest power consumption. There are various domains like the compiler optimization, application optimization, fabrication technology optimization and the microarchitecture concepts for power optimization to have reduction in power consumption. It seems now difficult to satisfy the greediness for speed by using the enhancement in the clock frequency only. Increasing speed by increasing number of cores in the processor design is the only way now to keep Moore's law alive. This is the reason why the whole focus of processor design and development is now on multicore and much-core processor philosophy. This paper is an attempt to suggest modification in the microarchitecture of the processor to have reduction in the power requirement. Some important conclusions based on the available test results are also derived after rigorous analysis. The investigation is based on the study and measurement already available regarding effect on power consumption with the variation of the various parameters such as number of cores, clock frequency and voltage level.

Keywords: Multicore processors, microarchitecture, power consumption